This invention relates in general to the field of integrated circuits and more particularly to an improved system and method for offset error compensation in comparators.
Integrated circuits formed on a substrate such as a silicon wafer often have offset errors introduced during the wafer fabrication process. These offset errors result from slight dimensional differences in integrated circuit components such as transistors. For example, a comparator may have a positive and a negative input each consisting of a transistor. A slight dimensional difference between the two transistors introduces an offset error into the comparator. The offset error may result in incorrect output. In addition, offset errors degrade both the linearity and the noise performance of the analog-to-digital converter in which the comparator is used.
Conventional systems for handling offset errors in integrated circuits include a cancellation scheme where the offset error is sampled and stored on a capacitor. The stored offset error is then used to cancel the offset error in the comparator. However, this cancellation scheme uses an extra clock cycle and limits clock speed thereby reducing the throughput of the comparator.
Another conventional technique for handling offset errors is the use of a dithering technique. This dithering technique adds a random noise source to an analog input to randomize the offset error. Random noise is added as a dithering source to improve the spurious free dynamic range. The disadvantage of the dithering technique is the random noise used as a dithering source is difficult to control and degrades the signal-to-noise ratio of the comparator. Therefore, it is desirable to handle offset errors in a more efficient manner.
From the foregoing, it may be appreciated that a need has arisen for a system and method for offset error averaging in comparators that provides improved linearity and increased speed. In accordance with the present invention, a system and method for offset error averaging in comparators are provided that substantially eliminate and reduce disadvantages and problems associated with conventional offset error compensation techniques.
According to an embodiment of the present invention, an offset error averaging system is provided that includes a comparator having an offset error, a positive receptor, a negative receptor, a positive output, and a negative output. A sequence generator generates a sequence of positive swap cycles and negative swap cycles. A first cross connect is coupled to the positive receptor, the negative receptor, a positive input signal, and a negative input signal. The first cross connect couples the positive input signal to the positive receptor and the negative input signal to the negative receptor in response to a positive swap cycle. In addition, the first cross connect couples the positive input signal to the negative receptor and the negative input signal to the positive receptor in response to a negative swap cycle. A second cross connect is coupled to the positive receptor, the negative receptor, the positive output, and the negative output. The second cross connect couples the positive receptor to the positive output and the negative receptor to the negative output in response to a positive swap cycle. In addition, the second cross connect couples the positive receptor to the negative output and the negative receptor to the positive output in response to a negative swap cycle.
The present invention provides various technical advantages over conventional systems for offset error compensation. For example, one technical advantage is providing improved linearity for comparators. Another technical advantage is to provide increased processing speed for the comparator. Yet another technical advantage is to minimize noise introduced into the circuit. Still another technical advantage is to minimize hardware needed for implementation of offset error compensation. A further technical advantage is in providing programmable control of the control sequence. Other technical advantages may be readily apparent to one skilled in the art from the following figures, description, and claims.